Journal of Electrical Engineering and Electronic TechnologyISSN: 2325-9833

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Research Article, J Electr Eng Electron Technol Vol: 4 Issue: 2

Temperature Dependent Sub threshold Drain Current Model for Junction less Gate all Around MOSFET with High-K Gate Stack

Suman Sharma1*, Rajni Shukla1 and M R Tripathy2
1Department of Applied Physics, Deenbandhu Chottu Ram University, Murthal, Sonepat, Haryana, India
2Department of Electronics and communication Engineering, Amity University, Noida, Uttar Pradesh, India
Corresponding author : Suman Sharma
Department of Applied Physics, Deenbandhu Chottu Ram University, Murthal, Sonepat, Haryana, India
E-mail:
suman.iitdelhi@gmail.com
Received: September 14, 2015 Accepted: November 09, 2015 Published: November 14, 2015
Citation: Sharma S, Shukla R, Tripathy MR (2015) Temperature Dependent Sub threshold Drain Current Model for Junction less Gate all Around MOSFET with High-K Gate Stack. J Electr Eng Electron Technol 4:2. doi:10.4172/2325-9833.1000118

Abstract

A temperature dependent sub threshold drain current model for junction less (JL) Gate all around (GAA) MOSFET with high-k Gate Stack is developed in this paper. Poisson’s equation in cylindrical coordinate has been solved using Parabolic Potential Approximation (PPA). The effect of temperature variation from 300-500 K on the sub threshold performance of the JL-GAA MOSFET by varying the gate stack thickness has been obtained using the proposed model. The developed model has also been used to study the Sub threshold- Slop of JL-GAA MOSFET at high ambient temperature. Band-gapnarrowing is also included in the analytical model as the doping concentration is very high. Atlas-3D device simulation tool has been used for the numerical simulations. Developed temperature dependent model for JL-GAA MOSFET with high-k dielectric has close agreement with the simulation results. Developed model is very useful for the device optimization; as the device dimensions reduces in radial direction the oxide thickness reduction becomes necessary and the use of high-k stack as a dielectric is demanded.

Keywords: Atlas-3D; Gate all around; High-k; Junction less; Modelling; Surrounding gate; Sub threshold slope; Short channel effects

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