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Hindi Research Article, J Electr Eng Electron Technol Vol: 5 Issue: 1
Design of Low Power CMOS Parallel Prefix Adder Cell
| Shaochen Yang, Lau KT* and Yufei Zhang | |
| School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore | |
| Corresponding author : Lau KT School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore E-mail: ektlau@ntu.edu.sg |
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| Received: November 22, 2015 Accepted: December 28, 2015 Published: January 05, 2016 | |
| Citation: Yang S, Lau KT, Zhang Y (2016) Design of Low Power CMOS Parallel Prefix Adder Cell. J Electr Eng Electron Technol 5:1. doi:10.4172/2325-9833.1000119 |
Abstract
Addition is the basic operation in many modern electronic applications. As the fastest adder, parallel prefix adder is of most interest for many circuit designers. For the past few decades, supply voltage and the size of transistors have been reduced tremendously. With more and more transistors being integrated on one single chip, the power issue must be taken care of. Low power adder has been studied for years and many solutions are proposed. In this paper, a new circuit is designed at transistor level. The proposed circuit cell employs transmission gate logic and a MUX-based structure. Simulations are conducted using Cadence® Virtuoso Spectre Simulator. The result shows that the new adder demonstrates a better performance in terms of power dissipation, which saves more than 5% energy compared with Conventional CMOS logic adders with different word length.
