The MOS chip fabrication and examine the major steps of the process flow. The emphasis will be on the general outline of the process flow and on the interaction of various processing steps, which ultimately determine the device and the circuit performance characteristics. There are very strong links between the fabrication process, the circuit design process and the performance of the resulting chip. Hence, circuit designers must have a working knowledge of chip fabrication to create effective designs and in order to optimize the circuits with respect to various manufacturing parameters. Also, the circuit designer must have a clear understanding of the roles of various masks used in the fabrication process, and how the masks are used to define various features of the devices on-chip. We begin with the well-established CMOS fabrication technology, which requires that both n-channel (nMOS) and p-channel (pMOS) transistors be built on the same chip substrate. The fabrication process is best understood by looking at how we fabricate a simple CMOS inverter on a piece of silicon. Journal of Electrical Engineering and Electronic Technology is a peer-reviewed scholarly journal in the field of electrical engineering and electronics that aims to publish the most complete and reliable source of information on the discoveries and current developments in the mode of research articles, review articles, case reports, short communications, etc. in all areas of electrical engineering and electronics and making them accessible online freely without any restrictions or any other subscriptions to researchers worldwide.