Multi-form, Multi-format Digital Comparator

Multi-form, Multi-format Digital Comparator

In this paper we analytically prove the possibility for synthesis of multi-form, multi-format digital comparator based on the unsigned comparison algorithm of binary numbers. The synthesized comparator is a new unique logical circuit, which is capable of comparing signed binary integers and binary fractions as well as binary-coded decimal numbers. This circuit is also capable of comparing floating-point numbers as represented in the IEEE-754 standard. The comparator is highly applicable since it integrates many different ways of representing the compared numbers by using this algorithm. It can successfully replace the traditional algorithm for comparison based on subtraction, which is used in digital processors. The comparator latency has been explored because it is necessary when the comparator is used in asynchronous control systems. The law of the latency distribution and its parameters has been defined.