Journal of Electrical Engineering and Electronic TechnologyISSN: 2325-9833

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Research Article, J Electr Eng Electron Technol Vol: 4 Issue: 1

Simplification of Incompletely Specified Sequential Machines

VC Prasad*
Faculty of Engineering, Dayalbagh Educational Institute, Dayalbagh, Agra -282005, India
Corresponding author : Prasad VC
Faculty of Engineering, Dayalbagh Educational Institute, Dayalbagh, Agra -282005, India (Retired from Indian Institute of Technology, Delhi, India)
E-mail: prasadvishdelhi@gmail.com
Received: February 20, 2015 Accepted: May 21, 2015 Published: May 25, 2015
Citation: Prasad VC (2015) Simplification of Incompletely Specified Sequential Machines. J Electr Eng Electron Technol 4:1. doi:10.4172/2325-9833.1000114

Abstract

Simplification of Incompletely Specified Sequential Machines

Most undergraduate books and research literature describe methods based on compatible sets to reduce the number of states of an incompletely specified synchronous/asynchronous sequential machine. Deviating from this, incompatible sets of states are used in this paper for this purpose. A simple technique is presented to generate all maximal incompatible (compatible) sets from compatible (incompatible) pairs of states. Generation of maximal incompatible sets has some advantages. 1) The largest set tells us about the number of states of the smallest machine. We can therefore know how “good” is the minimal machine. 2) We can know whether minimization is necessary or not. It is then minimized using an improved concept of minimality. Symbols of the states of the minimal machine are assigned to states in incompatible sets such that no two incompatible states get the same symbol. This approach gives a minimal machine compared to some methods for synchronous machines which try several possibilities. An example is given to show that a conventional minimal machine can be nonminimal with respect to the minimality introduced here. The improved minimality tends to give the smallest machine.

Keywords: Digital electronics; Sequential circuits; State minimization; Incompletely specified machines

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